The mathematics of a cyclic redundancy check, used to provide a quick check against transmission errors, are closely related to those of an LFSR. Both hardware and software implementations of LFSRs are common. However, an LFSR with a well-chosen feedback function can produce a sequence of bits that appears random and has a very long cycle.Īpplications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences. Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle. The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state. Thus, an LFSR is most often a shift register whose input bit is driven by the XOR of some bits of the overall shift register value. The most commonly used linear function of single bits is exclusive-or (XOR).
